This invention relates to a semiconductor memory device and, more particularly, to a clock synchronization semiconductor memory device.
In keeping up with the increasing operating frequency of a CPU, there is raised a demand for increasing the operating speed of a semiconductor memory device, such as a dynamic random access memory (DRAM). In order to meet this demand, a synchronization semiconductor memory device operating in synchronism with the external clocks exceeding 100 MHz, with a clock Period being tCK less than 10 ns, has made its debut. In the clock synchronization semiconductor memory device, the input/output and the operating timing of a-variety of control circuits are control led by clocks supplied from outside to enable operational control by commands (signal combination) and burst read/burst write with continuous accessing.
In the semiconductor memory device, when data is written from a writing circuit through a digit line in a memory cell selected on the memory cell array, a pre-set delay time is provided after the writing. After this delay time, pre-charging (with equalizing) from a pre-charging circuit to a digit line is executed to set the digit line at a pre-set potential. The pre-charging is executed after the pre-set delay as from the writing in order to prevent inputting of incorrect data which tends to occur if the pre-charging is executed before writing data in the memory cell. For the write recovery period of time, reference is made to, for example, the disclosure of the JP Patent Kokai JP-10-64269, the entire relevant disclosure thereof being incorporated herein by reference thereto.
In the case of the clock synchronization semiconductor memory device, the cycle from a clock (timing) at the last data writing until a clock (timing) of inputting a pre-charge command represents a write recovery period tWR, e.g., upon burst writing (likewise upon single writing). A digit line is pre-charged by inputting a pre-charge (PRE) command using a combination of control signals from an external terminal, whilst a word line is reset by resetting a row address line.
Thereupon, the reset timing of the internal row address strobe signal (RASB), that is the transition timing from the Low level to the High level, is delayed by a delay circuit, so that the word line connected to the memory cell will be reset after inputting the pre-charging command and subsequent data writing in a selected memory cell, whereby adjusting is performed on the timing of resetting of the word line selectively driven by an X-decoder (transition from the High level to the Low level).
Referring first to FIG. 13, schematics of an illustrative structure of an example of a conventional synchronous DRAM, as a clock synchronization semiconductor memory device, are explained. Meanwhile, in FIG. 13, those elements not directly related with the subject matter of the present invention, for example, a bank structure of a DRAM core, column address counter for burst control, burst length, burst type, CAS latency, mode register for storing an operational code or a refresh control circuit etc. are not shown for simplicity.
Referring to FIG. 13, the conventional synchronization DRAM includes a command decoder 11, which is fed with control signals from a row address strobe ({overscore ( )}RAS) terminal, a column address strobe ({overscore ( )}CAS) terminal, a write enable ({overscore ( )}WE) terminal and a chip select ({overscore ( )}CS) terminal, as output terminals, and which decodes commands from combinations of values of these control signals; an internal clock generating circuit 10 that generates an internal clock signal I CLK from an external clock signal input to a clock input (CLK) terminal; a mask signal generating circuit 12 that generates an internal DQM signal (signal controlling the masking of an input signal and output enable) based on a DQM signal fed from an input mask/ output enable (DQM) terminal; an internal address signal generating circuit 13 that inputs and buffers an address signal, selects a bank and outputs an internal address signal; an input/output circuit 14 that receives data from a data input/output (DQ) circuit and outputs data to the DQ terminal; an internal row address strobe signal generating circuit (internal RASB signal generating circuit) 15 that outputs an internal row address strobe (RASB) signal; a word line timing adjustment circuit 16; a CAS (column address strobe) control circuit 17, fed with an internal clock signal ICLK, a READ signal from the command decoder 11 and a write burst signal WBST; a RAS (row address strobe) control circuit 18, fed with the internal clock signal I CLK and an internal RASB signal; an X-decoder (XDEC) 19 fed with a row address from the internal address signal generating circuit 13 to decode the row address to select a word line; and a Y-decoder (YDEC) 20 fed with a column address from the internal address signal generating circuit 13 to decode the column address to select a digit line of a memory cell array.
An ACT (bank active) signal output from the command decoder 11 and a PRE (pre-charging) signal, output by the command decoder 11. are input to the internal RASB signal generating circuit 15 where an internal RASB signal is generated. Meanwhile, bank selection by a pre-set bit or bits of an address signal is made upon a bank active (ACT) command. After this ACT command, commands of read (READ), write (WRITE) and pre-charging (PRE) are executed.
This internal RASB signal generating circuit 15 is constituted by e.g., a set-reset (SR) latch circuit, such that, if an ACT signal is asserted, the internal RASB signal is rendered active (low-level), whereas, if the pre-charging (PRE) signal is asserted, the internal RASB signal, which has so far been active, is reset to an inactive (high-level) state.
This internal RASB signal is input to the word line timing adjustment circuit 16, which then generates an RAS3B (third row address strobe) signal controlling the word line strobe timing to supply the generated RAS3B signal to the X-decoder 19. The X-decoder decodes a row address signal to select a word line. If the RAS3B signal is turned active, the X-decoder 19 activates the selected word line, whereas, if the RAS3B signal is active, the X-decoder 19 resets the row address to reset the word line.
FIG. 14 schematically shows an illustrative structure of a memory cell array 21. A memory cell array transistor 22, connected to digit line pairs (D/DBxe2x80x941, D/DB xe2x80x942, . . . ) has its gate connected to a word line from the X-decoder 19. The digit line pairs are connected to a readout/write circuit (sense amplifier) 23 through a column switch on/off controlled by a column selection line from the Y-decoder 20. The readout/write circuit 23 is connected through an I/O line (read/write data bus) to the input/output circuit 14. In FIG. 14, 24 is a pre-charging equalizer circuit of the digit line pair receiving signals from the RAS (row address strobe) control circuit 18 of FIG. 13 to pre-charge and equalize the digit line Pairs. Here, the pre-charge potential of the digit line pairs (D/DBxe2x80x941, D/DBxe2x80x942, . . . ) is at an intermediate level of the power source potentials (amplitude of the digit line).
The word line timing adjustment circuit, configured as shown in FIG. 15, outputs the input internal RASB signal, which has turned low from the high level, at the same time, that is without delay, while outputting the internal RASB signal, which has turned high from the low level by the assertion of the PRE-signal, as a signal RAS3B delayed by delay time td provided by the delay circuit 301.
The X-decoder 19 is responsive to the resetting from the low level to the high level of this RASB3 signal to reset the row address. As a result, the selected word line is also reset from the high level to the low level to render the memory cells nonselected.
FIG. 16, illustrating schematics of the operation of the clock synchronization type semiconductor memory device, schematically shows the timing operation of a synchronous DRAM with a burst length equal to 4 clocks. That is, FIG. 16 schematically shows an external CLK terminal, a command, address, input data, an internal column address and a word line, in the sequence of operations of the bank active (ACT) command, called an xe2x80x9cACT commandxe2x80x9d, a write (WRITE) command, pre-charge command, called a xe2x80x9cPRE-commandxe2x80x9d, and a bank active command.
In FIG. 16(a), a write recovery period (tWR) is one clock cycle. When the PRE-command is entered, the PRE-signal turns active and the internal RASB signal goes to a high level, whereupon a signal delayed by a delay time td by a delay circuit 301 in the word line timing adjustment circuit 16 is output as an internal RAS3B signal, thereby to adjust the falling timing from the high level to the low level of the word line so as to reset the word line after the end of the write operation in the memory cell.
In the course of intense investigations toward the present invention, the following problems have been encountered. In the following a detailed analysis on the problems in the prior art will be given.
Meanwhile, as the operating frequency is increased to e.g 100 MHz, the clock period tCK is shortened, such that, as the p pre-charging period (tRP) of pre-charging the digit line, three clock cycles, for example, are required, as shown in FIG. 16(a).
In this case, if two clock cycles, for example, are taken as the write recovery period (tWR) in place of one clock cycle, the pre-charging period tRP remains unchanged, that is, it is three clock cycles. The last data DIN4 during burst writing, for example, is masked by the DQM signal, as shown in FIG. 16(b), with the write recovery period (tWR) being two clock cycles (2tCK). However, even in this case, a word line is reset after delay of the delay time (td) of the delay circuit 301 in the word line timing adjustment circuit 16 as from the time of inputting of the PRE-command, such that the pre-charging period tRP is three clock cycles, whilst it cannot be set to two clock cycles.
It is because the configuration is such that, even when the write operation for the memory cell has come to a close one clock cycle before the time point of inputting the PRE-command, the word line is reset after the delay td in the delay circuit 301 of the word line timing adjustment circuit 16 as from the time of inputting the PRE-command, such that the pre-charging of the digit line takes place after resetting of the selected word line, this delay time td being dragged (shifted) into the next following pre-charging period tRP.
Consequently, even when the write recovery period (tWP) is two clock cycles, it is not possible with the conventional synchronous DRAM to speed up the pre-charging period tRP.
Recently, there are raised a demand to use the synchronous DRAM with a write recovery period tWP=2 clock cycles and with a pre-charging Period tRP=2 clock cycles and another demand to use the synchronous DRAM with a write recovery period tWP=1 clock cycle and with a pre-charging period tRP=3 clock cycles, in meeting with a user application system.
However, with the above-described conventional synchronous DRAM, the pre-charging period tRP=three clock cycles needs to be maintained even in case with the write recovery period tWR=2 clock cycles, so that the above-mentioned demands by the user cannot be met with a sole synchronous DRAM chip. If the two demands are to be met, two sorts of the synchronous DRAM products need to be developed, thereby increasing the manufacturing cost of the semiconductor memory device.
In view of the above problems, it is a principle object of the present invention to provide a semiconductor memory device with which it is possible to speed up the pre-charging period (tRP).
It is another object of the present invention to provide a semiconductor memory device which realizes two modes, one mode being the write recovery period tWR=2 clock cycles with the pre-charge period tRP=2 clock cycles and the other being the write recovery period tWR=1 clock cycle with the pre-charge period tRP=3 clock cycles.
It is Yet another object of the present invention to provide a semiconductor memory device with which it is possible to speed up the RAS/CAS delay time as from a time point of inputting an active command until the inputting of a read command. Other objects and features of the present invention will become clear by the following description and the claims.
For accomplishing the above object, according to a first aspect of the present invention there is provided a clock synchronization semiconductor memory device comprising a variable control circuit (or in general, means for) variably controlling a period of time as from a time point of inputting a pre-charge command until resetting of a word line based on outcome of a determination as to whether or not a clock cycle at least one clock cycle before the time point of inputting a pre-charge command was under a write operation (i.e., corresponds to the timing of the write operation).
According to a second aspect, control is Performed so that, if the write recovery time tRP is used at two clock cycles, the falling timing from the High to the Low level of the word line after inputting a pre-charging command is quickened, whereas, if the write recovery time tWR is used at one clock cycle, the falling timing from the High to the Low level of the word line after inputting a pre-charging command is delayed.
According to a third aspect, the present invention also includes a variable control circuit (or, generally, means for) variably controlling a period of time as from inputting of a bank active command until activating a word line based on the results of check as to whether or not an internal row address strobe signal a pre-set number of clock cycles before the inputting of a bank active command is active.
According to a fourth aspect, the present invention is configured to perform control for checking (determining) whether or not a pre-charge command has been input a pre-set number of clock cycles before the time point of inputting of a bank active command. A switching control unit immediately activates a selected word line at a time points of inputting a bank active command if the pre-charge command is input the pre-set number of clock cycles before the time point of inputting the bank active command, to shorten the RAS/CAS (row address strobe/column address strobe) delay period tRCD as from the time point of inputting the bank active command until inputting a read command. On the other hand, the switching control unit activates the selected word line with a pre-set delay time as from the time point of inputting the bank active command if the pre-charging command is input the pre-set number of clock cycles before the time point of inputting the bank active command, to elongate the RAS/CAS (row address strobe/column address strobe) delay period tRCD as from the time point of inputting the bank active command until the inputting of the read command.
According to a fifth aspect, there is provided a clock synchronization semiconductor memory device comprising:
a determination circuit that determines whether or not a clock cycle at least one clock cycle before the time point of inputting the pre-charge command was under to a write operation; and
a variable control circuit that variably controls a period of time as from a time point of inputting a pre-charge command until resetting of a word line based on outcome of the determination means.
According to a 6th aspect, the clock synchronization semiconductor memory device comprises:
means for providing a pre-set delay time as from a time point of inputting a pre-charging command until resetting a word line, if the clock cycle at least one clock cycle before inputting a pre-charge command is under a write operation; and
switching controlling means for resetting the word line immediately in case the clock cycle at least one clock cycle before inputting the pre-charge command is not under the write operation.
According to a 7th aspect of the clock synchronization semiconductor memory device comprises:
a switching circuit that controls between introducing and not introducing a pre-set delay during the time as from a time point of inputting the pre-charge command until resetting of a word line, based on the state of an internal write enable signal during a clock cycle at least one clock cycle before inputting the pre-charge command.
According to an 8th aspect, the clock synchronization semiconductor memory device comprises:
checking means for checking whether or not a clock cycle at least one clock cycle before inputting a pre-charge command corresponds to a write operation;
means for storing results of the checking; and
means for variably controlling a period of time as from a time point of inputting a pre-charge command until resetting of a word line, at the time point of the inputting of the pre-charge command, responsive to the checked results.
According to a 9th aspect, the clock synchronization semiconductor memory device comprises:
checking means for checking whether or not a clock cycle at least one clock cycle before inputting a pre-charge command corresponds to a write operation and for storing results of checking;
time-delay means for providing a pre-set delay time as from a time Point of inputting a pre-charging command until resetting a word line if the results of check indicate that the clock cycle at least one clock cycle before inputting a pre-charge command corresponds to a write operation; and
a switching controlling means for resetting the word line immediately in case the results of check indicate that the clock cycle at least one clock cycle before inputting a pre-charge command does not correspond to a write operation.
According to a 10th aspect, the clock synchronization semiconductor memory device comprises:
checking means for checking whether or not the clock cycle at least one clock cycle before inputting a pre-charge command corresponds to a write operation, and also whether or not the input data is set to a masked state; and
switching controlling means for switching-controlling between introducing and not introducing a pre-set delay time as from a time point of inputting a pre-charging command until resetting a word line, at the time of inputting a pre-charging command, responsive to checked results of the checking means.
According to an 11th aspect, the clock synchronization semiconductor memory device comprises:
(a) a command decoder that decodes a command from a combination of control signals;
(b) an internal row address strobe signal generating circuit that generates an internal row address strobe signal responsive to inputting of a pre-charge signal supplied from the command decoder and a bank active signal; and
(c) a word line timing adjustment circuit that generates and outputs a word line strobe control signal configured to control strobe timing of a word line responsive to inputting of the row address strobe signal;
(d) the word line in the activated state being reset to an inactive state on transition of the word line strobe control signal from an active state to an inactive state;
(cc) the word line timing adjustment circuit comprises:
(c1) a delay circuit that receives the internal row address strobe signal and outputs the input signal with a delay; and
(c2) a switching control circuit that receives the row address strobe signal and a delayed output signal from the delay circuit and performs control responsive to a logical value of an internal write enable signal one clock cycle before as to whether or not transition from an active to an inactive state of the word line strobe control signal is to be delayed;
(c3) the switching control circuit setting a timing of transition from an active state to an inactive state of the word line strobe control signal to a timing delayed a delay time in the delay circuit from a timing of transition from the active state to the inactive state of the input row address strobe signal, if a value of the internal write enable signal one clock cycle before the inputting of the pre-charge command is active;
(c4) the control circuit performing switching control so that, if the value of the internal write enable signal one clock cycle before the inputting of the pre-charge command is inactive, the timing of transition of the word line strobe control signal from the active state to the inactive state is of the same timing as the timing of transition of the input row address strobe signal from the active state to the inactive state.
According to a 12th aspect, the clock synchronization semiconductor memory device comprises:
(a) a command decoder that decodes a command from a combination of control signals;
(b) an internal row address strobe signal generating circuit that generates an internal row address strobe signal responsive to inputting of a pre-charge signal output by the command decoder and a bank active signal; and
(c) a word line timing adjustment circuit that generates and outputs a word line strobe control signal controlling the strobe timing of a word line responsive to inputting of the row address strobe signal;
(d) the word line in an activated state being reset to an inactive state on transition of the word line strobe control signal from an active state to an inactive state; wherein;
(cc) the word line timing adjustment circuit comprises:
(c1) a delay circuit that receives the internal row address strobe signal and outputs the same with a delay as a delayed output signal;
(c2) a latch circuit that receives a line burst signal and a data mask signal and outputs and holds an active signal synchronous with internal clock signals only when the write burst signal is active and the data mask signal is inactive, with input data not being masked;
(c3) a first logic circuit that receives (i) an inversed signal of a delayed output signal from the delay circuit and (ii) an output signal of the latch circuit, as inputs, the first logic circuit outputting the delayed output signal of the delay circuit when an output signal of the latch circuit is active, the first logic circuit outputting a fixed value to mask the delayed output signal of the delay circuit when the output signal of the latch circuit is inactive; and
(c4) a second logic circuit that receives the internal row address strobe signal output by the internal row address strobe signal generating circuit and an output signal of the first logic circuit,
the second logic circuit operating responsive to the value of the output signal of the first logic circuit:
(i) either to output a signal transition of which from active to inactive is of the same timing as transition from active to inactive of the internal row address strobe signal, as the word line strobe control signal, or
(ii) to output, as the word line strobe control signal, a signal transition of which from active to inactive is delayed a delay time at the delay circuit from the transition timing of the internal row address strobe signal from active to inactive.
According to a 13th aspect, in the clock synchronization semiconductor memory device aforementioned with respect to 5th to 12th aspects,
the control is performed by switching over between first and second modes:
(1) the first mode being performed if a clock cycle immediately before the inputting of a pre-charge command is not a write operation, such that a write recovery time period is switched to two clock cycles and a pre-charge period is switched to two clock cycles; and
(2) the second mode being performed if a clock cycle immediately before the inputting of a pre-charge command is a write operation, such that the write recovery time period is switched to one clock cycle and the Pre-charge period is switched to three clock cycles.
According to a 14th aspect, the clock synchronization semiconductor memory device comprises:
(a) a determination circuit that checks as to whether or not an internal row address strobe signal a pre-set number of cycles before an inputting of a bank active command is active; and
(b) a variable control circuit that variably controls a period of time as from the inputting of a bank active command until activating a word line based on results of the checking.
According to a 15th aspect, the clock synchronization semiconductor memory device comprises:
(a) determination means for checking whether or not a pre-charge command has been input a pre-set number of cycles before a time of inputting a bank active command; and
(b) switching control means for switching over between first and second modes;
(b1) in the first mode. the switching control means immediately activating a selected word line at the time of inputting the bank active command if the pre-charge command is input the pre-set number of clock cycles before the time of inputting of the bank active command, to shorten a row address strobe/column address strobe delay period, termed as xe2x80x9cRAS/CAS delay periodxe2x80x9d, tRCD as from the time of inputting the bank active command until the inputting of the read command; and
(b2) in the second mode. the switching control means activating a selected word line with a pre-set delay time as from the time of inputting of the bank active command if the pre-charging command is input the pre-set number of clock cycles before the time of inputting the bank active command, to elongate the RAS/CAS delay period tRCD as from the time of inputting the bank active command until the inputting of the read command.
According to a 16th aspect, the clock synchronization semiconductor memory device comprises:
(a) a command decoder that decodes a command from a combination of control signals;
(b) an internal row address strobe signal generating circuit that generates an internal row address strobe signal responsive to inputting a pre-charge signal output by the command decoder and a band active signal; and
(c) a word line timing adjustment circuit that generates and outputs a word line strobe control signal for controlling the strobe timing of a word line responsive to inputting of the row address strobe signal;
(d) a selected word line being set to an active state on transition from an inactive to an active of the word line strobe control signal;
wherein
(cc) the word line timing adjustment circuit comprises:
(c1) a delay circuit that receives, as an input signal, the internal row address strobe signal and outputs the received input signal with a delay as an output signal;
(c2) a latch circuit that receives the internal row address strobe signal and outputs the internal row address strobe signal of a pre-set number of clock cycles before;
(c3) a first circuit that receives an output signal of the latch circuit and the output signal of the delay circuit to perform control responsive to a value of the internal row address strobe signal of a pre-set number of clock cycles before to permit passage of or mask of the internal row address strobe signal delayed by the delay circuit; and
(c4) a second circuit that receives the internal row address strobe signal and an output of the first circuit,
(i) if the internal row address strobe signal of a pre-set number of clock cycles before is active, the second circuit outputting, as the word line strobe control signal, a signal corresponding to the internal row address strobe signal, transition timing of which from an inactive to an active state is delayed a time equal to the delay time of the delay circuit from the transition timing from the inactive state to the active state of the internal row address strobe signal, so as to delay the transition from the inactive to the active of the word line, and
(ii) if the internal row address strobe signal of a pre-set number of clock cycles before is inactive, the second circuit outputting, as the word line strobe control signal, a signal corresponding to the internal row address strobe signal, transition timing of which from the inactive to the active state is the same as the transition timing from the inactive state to the active state of the internal row address strobe signal so as not to delay the transition from the inactive to the active of the word line.
According to a 17th aspect, the clock synchronization semiconductor memory device comprises:
(a) a command decoder that decodes a command from a combination of control signals;
(b) an internal row address strobe signal generating circuit that generates an internal row address strobe signal responsive to inputting a pre-charge signal output by the command decoder and a bank active signal; and
(c) a word line timing adjustment circuit that generates and outputs a word line strobe control signal for controlling strobe timing of a word line responsive to inputting of the row address strobe signal;
(d) a selected word line being set to an active state on transition from an inactive to an active state of the word line strobe control signal;
wherein
(cc) the word line timing adjustment circuit comprises:
(c1) a first delay circuit that receives the internal row address strobe signal;
(c2) a first latch circuit that receives the internal row address strobe signal to latch the received signal with internal clock signals;
(c3) a second latch circuit that latches an output of the first latch circuit with the internal clock signals;
(c4) a first logic circuit that receives, as input signals,
(i) an inversed signal obtained on inverting a delayed output signal of the first delay circuit via an inverter and
(ii) an output signal of the second latch circuit, either (i) to invertingly output the inversed signal received via the inverter from the first delay circuit, if an output signal of the second latch circuit is active, or
(ii) for the first logic circuit to output a fixed value to mask the inversed signal from the inverter if the output signal of the second latch circuit is inactive;
(c5) a second logic circuit that receives the internal row strobe signal output by the internal row address strobe signal generating circuit and an output signal of the first logic circuit, to output a NOR thereof;
(c6) a second logic circuit that receives an xe2x80x9coutputxe2x80x9d of the second logic circuit and delays this xe2x80x9coutputxe2x80x9d to issue the xe2x80x9cdelayed outputxe2x80x9d; and
(c7) a third logic circuit that outputs a NOR of the output of the second logic circuit and the output of the second delay circuit.